The present invention relates generally to a crosspoint switch, and, more particularly, to a crosspoint switch having a power-saving bias control circuit for controlling the bias current of each switch core as a function of switch state to minimize the power consumption of the crosspoint switch, and optionally having two memory cells associated with each switch core for reducing the reconfiguration time of the crosspoint switch.
Recent trends in data communications have necessitated the development of high-speed, reconfigurable data switches capable of routing signals to any of plural locations. Also, a known method for enhancing the processing power of a given technology is through the use of multiple processors sharing memory and input/output devices that are coupled together in a wideband communication network having a bandwidth in the range of multiple gigabits per second. In such applications, where the throughput rate of exchanging and sharing data needs to be maximized, it is desirable to have a non-blocking circuit switch that allows simultaneous data traffic at the network bandwidth. The key data routing function in such data networks is frequently performed by crosspoint switches, which allow incoming data streams to be routed to specified output channels.
Generally, a crosspoint switch for N-ports with N input and N output links consists of Nxc3x97N switch elements and corresponding latches that store switch setup or connection information provided by a switch controller. Crosspoint switches are used in many applications requiring reconfigurable high-speed switch networks. A crosspoint switch is an electronic circuit that is designed to receive one or more input signals at one or more input terminals and route the signals to one or more output terminals. A controller external to the switch network is generally used to reconfigure the crosspoint switch to change the routing of the input signals to different output terminals. The function of a crosspoint switch is shown schematically in FIG. 1, which is a simplified block diagram illustrating the matrix fabric of a 4xc3x974 array type crosspoint switch. Data inputs IN1-IN4 enter from the left-hand side through input buffers 10, and data outputs OUT1-OUT4 exit from the bottom through output buffers 12. Switch elements 14, which are typically pass-gate type elements such as FETs, provide reconfigurable, non-blocking paths from the inputs to the outputs.
The crosspoint switch is an important building block for digital communications systems that are required to share expensive resources. Such switches have been used in a wide range of systems, from workstations to computer networks, packet data networks and voice (circuit and packet) switching networks. Most recently, the shift towards graphical and video information display coupled with the widespread popularity of the Internet have significantly increased the demand for bandwidth and connectivity. Although this demand can be met by increasing the number of parallel connections in a given communication system, economic factors have favored increasing the bandwidth in each connection. This is especially true with respect to fiber optic lines, which provide a particularly high-speed data communications pathway with a wide bandwidth. As a result, there is significant demand in current network applications for crosspoint switches capable of delivering multi-gigabit per second performance for each channel.
While the telephone network was originally designed for voice communications, it has been evolving into a digital network for the transmission of audio, internet data and video data. During the 1980""s, new international broadband data communications standards for voice and data were formed. The resulting Synchronous Optical Network (SONET/North America), and Synchronous Digital Hierarchy (SDH/Europe and Asia) standards were defined to accommodate increasing bit rates. The baseline rate for SONET (OC-1) is 51.84 Mbps and the baseline rate for SDH (STM-1) is three times OC-1 or 155.52 Mbps. Currently, telcom networks operating up to OC-12 (OC-1xc3x9712) and OC-48 (2.5 Gbps) are in widespread deployment. Crosspoint switches are an integral part of such networks. Crosspoint switches for OC-12 and lower bit rates can be readily realized with silicon-based BJT or CMOS VLSI technology. One such crosspoint switch which is commercially available is model TQ8025, available from Triquint, the datasheet of which is incorporated herein by reference. At bit rates in the multi-gigabit per second range, various approaches have been used to combat effects associated with high-frequency communications, such as excessive power dissipation, jitter and crosstalk.
The explosive demand for broadband Internet access has fueled the need to increase the bandwidth of telcom networks. At present, GaAs laser drivers, preamplifiers and the like are capable of addressing bit rates of over OC-48 (2.488 Gbs) and OC-192 (9.953 Gbs), and advanced III-IV technologies are addressing OC-768 (39.13 Gbs) and higher. Crosspoint switches capable of accommodating these bit rates are needed to transform a link into a network in order to meet the connectivity requirement.
FIG. 1 illustrates the most natural realization of a crosspoint switch, which is the so-called matrix or array architecture. In the matrix architecture, a matrix of n inputs by m outputs is interconnected with switch elements 14 at each intersection. FIG. 2 is a simplified block diagram illustrating a typical crosspoint switch 200 having a matrix architecture. The crosspoint switch 200 includes input terminals IN1-INN coupled to receive corresponding input signals. The crosspoint switch 200 also includes output terminals OUT1-OUTN, to provide corresponding output signals. The crosspoint switch circuit 200 is used to selectively route one or more of the input signals received at the input terminals IN1-INN to one or more output terminals OUT1-OUTN. An input buffer 202 is connected to each input terminal IN1-INN, the output of which is connected to an input lead of each of a row of substantially identical switch cores 204. Thus, each input terminal is connected to all of the switch cores 204 in a given row. Similarly, each output terminal OUT1-OUTN is connected to all of the switch cores 204 in a corresponding column of switch cores 204 through an output buffer 206. A switch configuration control circuit 208 has an input port 210 coupled to receive configuration control signals CONFIG from an external controller (not shown), through which the external controller configures each crosspoint switch core 204. The configuration control signals CONFIG are typically serial multi-bit signals that include the configuration information on an input-to-output basis (i.e., for each input signal, the configuration control signals CONFIG control which output terminal or terminals the input signal is to be routed to). Of course, the control signals can be multi-bit parallel signals. In response to the configuration control signals, control logic in the switch configuration control circuit 208 configures each switch core 204 to select one of the input signals and provide an output signal dependent on the selected input signal to output terminals OUT1-OUTN, respectively. In some applications of the crosspoint switch 200, one or more of input terminals IN1-INN and one or more of output terminals OUT1-OUTN are not used.
As a general rule, no two inputs of the crosspoint switch can be routed to the same output at the same time. This would constitute a contention. However, one input can be connected to several outputs. This is referred to as the broadcast mode. In either case, the total number of switches that are actually routing data for a 16xc3x9716 switch is no more than 16. In any given configuration, no more than 16 switches are always on.
To configure each switch core 204, switch configuration control circuit 208 includes output leads (not shown) respectively connected to each switch core 204. The switch configuration control circuit 208 provides a select signal to configure each switch core 204.
Referring to FIG. 3, the structure of the switch cores 204 in a typical matrix type crosspoint switch 200 and the manner in which the switch cores 204 are controlled by the switch configuration control circuit 208 is now described. In FIG. 3, the switch configuration control circuit 208 is represented by individual blocks labelled xe2x80x9cSwitch State Controlxe2x80x9d to illustrate the individual control of each switch core performed by the switch configuration control circuit 208. As will be appreciated, in a conventional matrix type crosspoint switch, the structure performed by the xe2x80x9cSwitch State Controlxe2x80x9d blocks shown in FIG. 3 is contained in the switch configuration and control circuit 208. As is typical of crosspoint switches designed for use in high speed applications, the input signals and output signals are differential signals. Also, the switch core 204 of the crosspoint switch 200 comprise two-level differential amplifiers, and the configuration control signals output by the switch configuration control circuit 208 are differential signals.
Each of the switch cores 204 has a bias transistor Q1300 which has an emitter connected to a power source VSS 302 (which is ground potential in the example shown in FIG. 3) through a resistor 304. The base of the bias transistor Q1300 is connected to a bias voltage Vbias which has a level dependent upon the nature of the transistors used in the switching core 204. The bias voltage Vbias is applied at all times during operation of the crosspoint switch 200, even when the respective switch core 204 is OFF (not routing an input to an output). The collector of the bias transistor Q1300 is connected to a lower differential pair 306 comprised of transistors Q2 and Q3. The lower differential pair 306 is used for current steering and controls the output state of the respective switch core 204 by diverting current through either one of a top differential pair 308 formed of transistors Q4 and Q5 (switch xe2x80x9cONxe2x80x9d) or supply voltage (switch xe2x80x9cOFFxe2x80x9d). In the top differential pair 308, the transistor Q4 has its base connected to a respective one of the differential input signals INK through a corresponding input buffer 202 and its emitter connected to the collector of the transistor Q2. Transistor Q5 of the top differential pair has its base connected to the other of differential input signal INK through an input buffer 202 as shown in FIG. 2 and its emitter connected to the collector of the transistor Q2. The collectors of the transistors Q4 and Q5 are connected to a respective one of the output pairs OUT1-OUT16. As can be seen, the collectors of the top differential pair of each of the switch cores are also tied to pull-up resistors 310 and 312, respectively. Each switch core 204 connected to the same output has the same structure, and the outputs of each switch core 204 connected to the same output line are thus arranged in a xe2x80x9cwired ORxe2x80x9d configuration.
When the switch core 204 is in an ON state, the bottom differential pair 306 formed of the transistors Q2 and Q3 serves to divert current through the top differential pair 308 formed of the transistors Q4 and Q5 so that the top differential pair 308 transfers the differential input signals to the output during the xe2x80x9cONxe2x80x9d state of the switch. When the switch core 204 is in an OFF state, the bottom differential pair 306 serves to divert current from the positive supply through the bias transistor Q1300.
Due to the large number of independently driven switches, the matrix design crosspoint switch is inherently non-blocking and has the ability to broadcast each input to as many outputs as desired. At relatively low bit rates, the matrix architecture is best realized with FET or CMOS technology where pass gates are used as the switching elements. The primary advantage of the matrix type crosspoint switch is its potential to pass both small-signal analog and digital signals since the xe2x80x9cONxe2x80x9d FET can be thought of as a somewhat linear low-value resistor connecting an input to an output. The matrix architecture is extensively employed in commercial low-speed analog/digital switches.
At high speeds, the matrix architecture has several key limitations for digital signals. Since the input and output lines need to be connected to a larger number of nodes, the interconnect lines tend to be long which results in a large capacitance that is difficult to drive at a high speed with low jitter. In addition, both the input and output interconnects are attached to a large number of xe2x80x9cOFFxe2x80x9d devices, which further increases the load capacitance of the driving stage. In the pass-gate configuration, the active device does not have much gain or drive capability; thus, the input drive stage needs to drive all of the parasitic capacitance from the input to the output. The situation can be significantly improved by placing buffers between each crosspoint; however, this further increases the size, transistor count, power dissipation and complexity of the circuit. Due to these limitations, many high-speed crosspoint switches use alternative designs.
Accordingly, there is a need for a matrix architecture capable of providing high-speed bit rates which overcomes the foregoing problems.
The so-called multiplexer type crosspoint switch is a conventional alternative to the matrix architecture employed in high-speed crosspoint switches. In a multiplexer type crosspoint switch, the inter-stage buffering and the switching functions are combined into one stage through the use of digital multiplexers (MUXes). A multiplexer (MUX) serves to route one of its inputs to a selected output based on the control code provided. FIG. 4 illustrates the topology of a typical 16xc3x9716 crosspoint switch 400 using sixteen 16:1 MUXes 402 connected in parallel. The crosspoint switch 400 includes input terminals IN1-IN16 coupled to input buffers 404 to receive input signals. The crosspoint switch 400 also includes output terminals OUT1-OUT16, where the crosspoint switch 400 provides output signals. The crosspoint switch circuit 400 is used to selectively route one or more of input signals received at the input terminals IN1-IN16 to one or more output terminals OUT1-OUT16 through output buffers 406.
In the multiplexer type crosspoint switch 400, each input terminal IN1-IN16 is connected to a corresponding input lead of each of sixteen substantially identical 16:1 multiplexers 402, so that each input terminal IN1-IN16 is connected to all of the multiplexers 402. A MUX configuration control and memory circuit 408 has an input port 410 coupled to receive configuration control signals CONFIG from an external controller (not shown), through which the external controller configures the crosspoint switch circuit 400. The configuration control signals CONFIG are typically serial multi-bit signals that include the configuration information on an input-to-output basis (i.e., for each input signal, the control signals control which output terminal or terminals the input signal is to be routed to). Of course, the configuration control signals CONFIG can be multi-bit parallel signals. In response to the configuration control signals, the MUX configuration control and memory circuit 408 configures each multiplexer 402 to select only one of the input signals and provide an output signal dependent on the selected input signal to one or more of the output terminals OUT1-OUT16, respectively. In some applications of the crosspoint switch 400, one or more of input terminals IN1-IN 16 and one or more of output terminals OUT1-OUT16 are not used.
To configure each multiplexer 402, the MUX configuration control and memory circuit 408 includes output leads 4121-41216 respectively connected to a select input lead SEL of the multiplexers 402. The MUX configuration control and memory circuit 408 provides a 4-bit serial select signal to configure each multiplexer to select one of the 16 input terminals IN1-IN16. In an Nxc3x97N crosspoint switch, each select signal is typically a K-bit signal (where N=2K) so that the MUX configuration control and memory circuit 408 configures each multiplexer 402 to select one of N input signals IN1-INN. Multiplexers 402 then output the selected signals to the output terminals, respectively.
The MUX architecture is virtually identical to the matrix architecture with a MUX 402 replacing one of the output legs in the matrix. Each output OUT1-OUT16 is driven by one multiplexer 402 that has access to each of the 16 inputs. Since each output has its own multiplexer 402, the crosspoint switch 400 is both non-blocking and has the ability to operate in broadcast mode, where one input is connected to several outputs. Furthermore, unlike the matrix type architecture where each switch core needs to be independently switched, each multiplexer is digitally programmable. This allows simplification of the control logic.
FIG. 5 illustrates the basic structure of the switch core of a typical 2:1 MUX of a multiplexer type crosspoint switch. In the crosspoint switch 400 of FIG. 4, each multiplexer 402 routes each of the inputs to a selected output. Inside each 16:1 multiplexer 402, a stacked configuration of differential pairs is used. A bottom differential pair 500 comprising transistors Q8 and Q9 diverts bias current from one of two top pairs 502, 504. A first top differential pair 502 formed of transistors Q12 and Q13 routes a selected input INK to a selected output and a second top differential pair 504 comprising transistors Q10 and Q11 routes another input INJ to the output. This is a typical embodiment of a 2:1 MUX. By stacking a third pair, a 4:1 MUX can be implemented. Although stacking can be indefinitely extended in theory, power supply levels limit the stack size. For example, 3-4 level stacks are common in a 5.2V system. The recent trend in crosspoint switches is to lower power supply voltages (e.g., 3.3V), which does not allow for more than 2 or 3 levels of stacks. Larger multiplexers are thus constructed by cascading several lower order MUXes. For example, FIG. 6(a) shows the construction of a 4:1 MUX using 3 2:1 MUXes, and FIG. 6(b) shows the construction of a 16:1 MUX using 5 4:1 MUXes (or 15 2:1 MUXes. Cascaded approaches typically have improved performance over, for example, a one-stage 16:1 multiplexer at the expense of increased power dissipation. For instance, the power dissipation of a 4:1 MUX is the sum of the power dissipation of all three 2:1 MUXes. Since each differential pair is in use at all times, however, there is no margin for power management. Thus, multiplexer type crosspoint switches typically require a higher operating voltage level than array type crosspoint switches.
The main function of a crosspoint switch is to provide reconfigurable, user-specified routing paths from a set of inputs to a set of outputs. To perform this function, some form of memory storage is typically associated with each crosspoint switch core to store a current routing configuration pattern. The memory contents are used to open or close switches in the switching array. A one bit memory can be associated with each of these switches and if the bit is at a logic xe2x80x9c1xe2x80x9d level, for example, then the switch is ON and at a logic xe2x80x9c0xe2x80x9d level, the switch is OFF. Of course, the logic level used to turn switch elements ON and OFF will vary depending upon the conductivity type of the transistor element used to implement the switch. In actual implementations, the memory requirement of the crosspoint switch elements is optimized through the use of coding. For example, a 16xc3x9716 matrix type crosspoint switch has 16 inputs and 16 outputs, with each of 16 MUXes requiring 4-bits of memory storage. The 16xc3x9716 MUX corresponds to 256 individual switch cores in an array architecture. Memory requirements for switch configuration storage in a 16xc3x9716 crosspoint switch thus vary from 64 bits to 256 bits.
The rate at which the crosspoint switch configuration is changed is typically several orders slower than the maximum data speed. In a typical environment, the configuration of the switch is set up by loading the configuration bits from a protocol processor (for packet networks) that decodes the packet addresses and the switch is then used for routing data in accordance with the pre-set configuration. In circuit switched telephone networks, the configuration bits are set by the call setup control logic. Thus, a small interruption in routing is presented when the switch configuration is altered.
While several implementations have been proposed for crosspoint switches, switch elements for high-speed applications (in the gigabit per second range) are generally implemented using bipolar, GaAs, FET or HBT technology to accommodate the need for handling high-speed switching. Input buffers are used to present a lower capacitance to the outside and drive the switch array. Output buffers provide the drive necessary to support the external load while presenting a low capacitance to the switch array. Bias circuits and configuration logic make up the remainder of the crosspoint switch, and configuration logic is generally implemented using CMOS transistors (for Silicon BiCMOS and SiGe BiCMOS technologies) and thus occupies a small space and dissipates little power. In GaAs technology, implementations of logic cannot take advantage of CMOS circuits. For high-speed implementations (in the Gbps range), inputs and outputs are usually implemented with differential circuits having 50xcexa9 terminations. Internal circuits also use a differential configuration but not necessarily at a 50xcexa9 impedance level. In addition, at high speeds, the switching transistors must be biased at high current levels, typically on the order of several mA. While lower speeds permit the use of pass-gate transistor type switches, differential amplifier type circuits are normally required to implement high-speed switches. The configuration and control circuits are usually implemented with lower power biasing or with CMOS circuits, which is well suited for logic and memory implementation, because the speed requirements are at least an order of magnitude lower.
Crosspoint circuits operating at high speeds dissipate large amounts of power because the transistors used for switching are biased at high currents to enable them to achieve high switching speeds. In some high-speed crosspoint switch circuits, the high-speed circuitry implementing the crosspoint switch cores has a significant static power dissipation (i.e., the power dissipation of the circuitry while in a static or non-transitioning state). A typical switch used in data/packet switching can be of the size 16xc3x9716 or larger. Usually, switching systems use several such chips in an array configuration to implement large switching capabilities. The size of the switch realized on a chip is usually limited by the number of available pins, the power dissipation of the switch array, and the yield that can be obtained during manufacture. If switches can be implemented at lower power, the chip size and cost of the packaging can be lowered and the size of the switch is limited only by the number of required pins and manufacturing considerations.
In the gigabit per second range, most known implementations use either the array type architecture or the multiplexer type architecture having switch implementations as shown in FIGS. 1-3 and FIGS. 4-6(a) and 6(b), respectively. In the array architecture (FIG. 3), Q1 is the bias transistor, and the bottom differential pair 306 comprised of transistors Q2 and Q3 control the switch state by diverting the current through the top differential pair 308 Q4 and Q5 (switch xe2x80x9cONxe2x80x9d) or to the positive supply (switch xe2x80x9cOFFxe2x80x9d). The top differential pair 308 transfers the inputs to the outputs during the xe2x80x9cONxe2x80x9d state of the switch. A major disadvantage of this approach is that the switch cores are always biased, even when they are in an OFF state. The total static power dissipation of the chip can be approximated by the following Equation (1):
xe2x80x83Total Power Dissipation=256xc3x97(Ibiasxc3x97Vbias)+Pdiss (control and config. circuit)+Pdiss (input and output buffers)+Pdiss (bias circuits)xe2x80x83xe2x80x83(1)
wherein Ibias is the transistor bias current and Vbias is the transistor bias voltage of transistor Q1.
At high speeds, Ibias is high and the total static power dissipation becomes large. Particularly, in the gigabit per second range, the power dissipation of the switch cores becomes the dominant factor in the above-expressed equation. The power dissipation of the conventional crosspoint switch in high speed applications is on the order of 5 Watts, which necessitates expensive chip layout, special packaging considerations to accommodate the high power dissipation of the switch, and higher demands on reliability of the chips.
In the multiplexer architecture (FIGS. 4-6(a) and 6(b)), for instance, multiplexers are formed of a stacked configuration of differential pairs (FIG. 5). The bottom differential pair 500 comprising transistors Q8 and Q9 diverts bias current from one of the top two pairs. One of the two top differential pairs 502 (transistors Q12, Q13) routes a first input INK to an output. The other top differential pair 504 (transistors Q10, Q11) routes a second input INJ to the output. This is a typical embodiment of a 2:1 MUX. By stacking a third pair, a 4:1 MUX is implemented, and cascading is used as shown in FIG. 6(b) to produce the 16:1 MUXes 402 shown in FIG. 4. The power dissipation of a 4:1 MUX comprising three stacked 2:1 MUXes is the total power dissipation of each of the individual MUXes. Since each differential pair is in use at all times, there is no margin for power management. Assuming that a 3 level stack implementation is used to realize a 4:1 MUX, and that a 16:1 MUX will require 5 such 4:1 MUXes, the total static power dissipation of such an implementation may be approximated by the following Equation (2):
Total Power Dissipation=16xc3x97(5xc3x97Ibiasxe2x88x924:1 MUXxc3x97Vbias)+Pdiss (control and config. circuit)+Pdiss (input and output buffers)+Pdiss (bias circuits)xe2x80x83xe2x80x83(2)
wherein Ibiasxe2x88x924:1 MUX is the bias current of each of the five 4:1 MUXes cascaded to form the 16:1 MUX, and is equal to 15 times the bias current of each of the cascaded 2:1 MUXes forming the 16:1 MUX.
Using this approach, the total static power dissipation of the multiplexer type crosspoint switch is slightly lower than that of the matrix architecture. Since the 16:1 MUX comprises 5 4:1 MUXes and 15 2:1 MUXex, the first factor in equation (2) is equivalent to 256xc3x97the bias current (xc3x97VEE) of the 2:1 MUX. While power dissipation at a given power supply voltage is slightly lower in the (MUX) architecture than the array architecture, the minimum power supply voltage of the multiplexer architecture is typically higher. MUX architecture based switches can be implemented using lower power supply voltages but at the expense of increased cascaded 2:1 Muxes and hence increased power dissipation. The delay through the system is proportional to the number of cascaded stages. In the 16xc3x9716 switch described above, 2 stages of 4:1 MUXes are used for realizing the 16:1 MUXes. The assumption of a 3 level stack is subject to the condition that adequate room is available in the power supply system. With a 3.3 V system, a 3 level stack would not be easy to implement if adequate room for voltage swing margins must be maintained.
Other major disadvantages are caused by the high power dissipation of conventional crosspoint switch architectures. While actual power dissipation depends on the choice of semiconductor technology and choice of power supply voltage levels, typical high-speed crosspoint switches have a total power dissipation level on the order of several Watts. Such devices have expensive packaging requirements, and generally require active cooling and ceramic packaging. At a power dissipation of about 1 Watt, the cost of packaging may be reduced significantly since active cooling and ceramic packaging can be avoided. High power dissipation also increases chip area, in that circuit wiring, and most notably power supply wiring, must be made wide enough to carry the several amperes of current necessary to drive the switch elements at the necessary switching rates. Utilizing single crosspoint switch chips as a building block, it is desirable to produce large switching matrices (for instance, in SONET applications). For example, 512xc3x97512 switches are not uncommon in current applications. A power dissipation per chip of several Watts requires individual chips to be spaced apart significantly to facilitate heat removal. Reduced power consumption can thus make a big difference in the cost and complexity of a given system. For a power dissipation of each module of more than 1 Watt, a given system increases in size and in capacitive and inductive loading to the input and output lines. Chips which dissipate several Watts typically have one-half their total number of pins/solder balls dedicated to the supply of power and ground lines to the chip. A reduction in power level of a chip from 5W to 1W allows a substantially lower the total pin/ball count.
Since there is only stage between each input and output in the array architecture, the delay from input to output is minimized. In the MUX architecture, delay is usually larger and is a function of the number of cascaded stages. Increased delay per chip can present obstacles in the design of large switch matrices using several chips.
In accordance with the present invention, a power-saving bias control circuit is provided in a crosspoint switch for controlling the bias of individual switch cores of the switch so that the respective switch cores are unbiased when not in use according to a given switch configuration. This reduces the static power dissipation of the crosspoint switch and enables the production of crosspoint switches having an increased number of switch cells with a reduced overall size.
In one embodiment, a matrix type crosspoint switch capable of being configured to reduce static power dissipation is provided. The crosspoint switch includes a plurality of input terminals, a plurality of output terminals, a plurality of input lines each being connected to a respective input terminal, a plurality of output lines each being connected to a respective output terminal, a plurality of switch cells connected to the input lines and the output lines, each switch cell containing a switch core for selectively connecting an input terminal to an output terminal and a bias control circuit for controlling a bias supplied to the switch core. The switch cores each have a control terminal and are arranged so that an input signal at any one of the input terminals may be routed to any one of the output terminals. The bias control circuit is configured to receive configuration information from an external controller and is responsive to the configuration information to provide a signal to the switch core to disable the switch core to substantially reduce the static power dissipation of the respective switch core.
Accordingly, the static power dissipation of disabled switch cells of the crosspoint switch is eliminated. The bias control circuit receives configuration information from an external controller and configures the switch cells in response to the configuration information. When configuring the switch cells, if instructed to do so, the bias control circuit selectively disables one or more of the switch cells, thereby substantially reducing the static power dissipation of the selectively disabled switch cell.
Although additional circuitry is added to each switch cell according to the present invention, the added complexity of the bias control circuit and the power consumption thereof result in a substantial reduction in overall power consumption of the crosspoint switch enabling the production of a crosspoint with greatly reduced power consumption than available with known implementations. Moreover, the additional circuitry is preferably implemented using CMOS transistors, to add only a small area overhead to the entire chip.
In another embodiment, a memory cell for storing two bits of data is added to each switch cell to provide for fast reconfiguration. A first memory bit is provided for storing a current switch configuration and a second memory bit is provided for storing a subsequent switch configuration. Thus, the present invention achieves a faster crosspoint switch having an overall power savings and a lower cost design.
By the foregoing structure, a reduction in power dissipation of a crosspoint switch from several Watts to approximately 1 Watt can be achieved, to thereby substantially reduce the cost of packaging by eliminating the need for active cooling and ceramic packaging of the crosspoint switch. In addition, the size of the wiring may be substantially reduced since the wiring layers need not be wide enough to carry large currents. When utilizing a crosspoint switch circuit according to the present invention as a building block for a network to produce larger switching matrices, the a lower power dissipation of the inventive crosspoint switch results in a substantial reduction in cost and complexity since the power dissipation of each module is reduced, thereby allowing devices to be placed closer, which avoids an increase in capacitive and inductive loading to the input and output lines.